The present invention relates to integrated circuit structures and fabrication methods, and specifically to the formation of conductive plugs for interconnects.
Background: Contact and Via Hole Filling
As integrated circuits are scaled to smaller submicron dimensions, the geometries of contact and via holes become more difficult to work with. The vertical spacings of the layers do not shrink as fast as the horizontal dimensions, so the aspect ratio (height to width ratio) of contact and via holes is continually increasing. Secondly, as the width of contact holes becomes smaller, the ratio of sidewall surface area to hole volume becomes larger.
Background: Plug Processes
One of the standard tools for contact and via metallization is a plug process. In such processes, a conductive material is used to substantially fill the contact hole before the overlying conductor layer is deposited in the pattern. Even if the contact or via hole is only filled partway, the ability to partially fill the volume of the hole greatly eases the requirements on the following metallization step. Thus a material, such as tungsten or polysilicon, which has a very good conformal deposition process can be used for the conductive plugs, and the overlying metallization layer can be a material (such as aluminum or an aluminum alloy) which is selected for other reasons.
Traditionally, recessed polysilicon plugs were fabricated using reactive ion etch (RIE). However, step height uniformity of the recessed structures fabricated by RIE is relatively poor. The process flow using traditional RIE is shown in FIGS. 3A and 3B. First, polysilicon 30 is deposited on top of the dielectric 10 to fill holes (FIG. 3A). In general, the as-deposited polysilicon surface is not planar. Next, a recessed structure is formed when the necessary overetch (required to ensure that all polysilicon is removed from the dielectric surface) removes some polysilicon from the hole (FIG. 3B). The minimum step height of the recessed structure is limited by the step height of the as-deposited surface, the difference of etch rates between the dielectric and polysilicon, and the total etch time. In general, this process gives high non-uniformity within a wafer.
Formation of Conductive Plugs with Precisely Controllable Protrusion Above Contact Holes
The present invention provides a new method for fabrication of recessed plugs in contact or via holes. Before the contact or via holes are patterned, an oxidation-resistant material is deposited over the dielectric. This layer is patterned and etched, together with the interlevel dielectric, to define the contact holes. Thereafter, a conductor is deposited into the contact or via hole, the conductor being of an oxidizable material (at least in its upper portion). In the presently preferred embodiment, the oxidizable material is polysilicon. Thereafter, a selective CMP process is performed, which polishes away any excess of the plug material above the top of the oxidation mask material, but which is highly selective to the oxidation mask material. Thus, the oxidation mask material is not eroded when the polishing operation is performed. This is followed by a controlled oxidation step, to oxidize the conductor to a controlled distance below the top of the oxidation mask. An etching process is performed to remove the oxidized conductor material, very selectively with respect to the oxidation mask material and the unoxidized conductor material. This process forms a recessed conductive plug with a very controllable step height, in contrast to the previous methods employed.
Advantages of the disclosed methods and structures include:
improves step height uniformity across wafer and within lot; PA1 better process control because step height is only determined by the thickness of thermally oxidized polysilicon; PA1 uses currently available processes; PA1 lower cost of ownership due to higher throughput and lack of RIE.